This application claims the benefit of Korean Patent Application No. 2000-8041, filed on Feb. 19, 2000, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a thin film transistor-liquid crystal display (TFT-LCD) device. More particularly it relates to a method of preventing overetching a data pad when fabricating an array substrate for use in the TFT-LCD device.
2. Discussion of the Related Art
In general, an LCD device is divided into a display part and a pad part. The display part of an LCD device is typically made up of a liquid crystal interposed between two substrates. One substrate, referred to as an array substrate, includes a matrix array of thin film transistors (TFTs) as switching devices and pixel electrodes. The array substrate also includes gate and data lines having gate and source electrodes, respectively. The gate and data lines cross each other. The opposing substrate, referred to as a color filter substrate, includes a light-shielding film (also known as a black matrix), a color filter, and a common electrode.
The pad part of an LCD device includes gate pads and source pads applying signal voltage and data voltage to the gate lines and the data lines, respectively. The gate pads are arranged on one side of the array substrate and the source pads are arranged on an adjacent side of the gate pads.
To make the array substrate described above, a depositing technique, a photolithography technique, and an etching technique are repeated several times. The specific method of etching is determined by the substance that is etched. Of these, the etching technique includes dry-etching and wet-etching. Dry-etching isotrophically etches an object, while wet-etching anisotropically etches it. Dry-etching generally uses gases, while wet-etching uses acids and other chemical solutions as an etchant. In chemical dry-etching, for example plasma dry-etching, plasma is used to generate gas radicals in order to etch any portions of a thin film. In physical dry-etching, for example ion beam milling etching, an ion beam is used in order to etch any portions of a thin film.
Referring to the attached drawings, an array substrate of an LCD device that is manufactured by a conventional method will now be explained in some detail.
FIG. 1 is a partial plan view illustrating an array substrate manufactured according to a conventional method of fabricating a TFT array substrate using a four-mask process. As shown in FIG. 1, the array substrate 8 of the LCD device includes, for example, TFTs xe2x80x9cAxe2x80x9d, pixels xe2x80x9cPxe2x80x9d, gate pads 11, gate lines 13, data pads 15 and data lines 19. Each TFT has a source electrode 17, a drain electrode 18, a gate electrode 10 and an active layer 16 as a channel region. The gate electrode 10 extends from the gate line 13 and the source electrode 17 extends from the data line 19. The drain electrode 18 is spaced apart from the source electrode 17. The gate and data pads and 15 act to apply the signals. Although not recognized in FIG. 1, the data pads 15 are formed in later process steps than the gate pads 11 so that the data pads 15 positioned above the gate pads 11.
The steps of forming the elements shown in FIG. 1 will be explained with reference to FIGS. 2A to 2D, hereinafter. FIGS. 2A to 2D are cross-sectional views taken along lines Ixe2x80x94I, IIxe2x80x94II and IIIxe2x80x94III of FIG. 1 and illustrate manufacturing process steps of the array substrate according to the conventional art
As shown in FIG. 2A, a first metallic material such as Aluminum (Al), Al-alloy, Chrome (Cr) or Tungsten (W) is deposited on the substrate 9. And then the first metal layer is patterned in a designed shape by a photolithography process using a first mask. During the photolithography process, a photoresist (not shown) is first formed on the first metal layer and then an exposure process is performed using the first mask. After that, portions of the photoresist, which are irradiated, are removed, and the exposed portions of the first metal layer are then etched. Next, the remaining photoresist is removed. Finally, the gate line (see element 13 of FIG. 1), the gate electrode 10 extended from the gate line, and the gate pad 11 arranged at the end of the gate line 13 (see FIG. 1) are formed. Then, a first insulation layer 26, a semiconductor layer 27 including intrinsic and extrinsic semiconductor, and a second metal layer 24 are sequentially formed on the substrate 9 and over the patterned first metal layer.
Referring to FIG. 2B, a second mask process is performed. The second metal layer 24 (see FIG. 2A) is patterned by the photolithography process described above. Thus, the data line 19, the source electrode 17, the drain electrode 18 and the data pad 15 are formed. The data line 19 is formed on the semiconductor layer 27, and the source electrode 17 is extended from the data line 19 and overlaps one end portion of the gate electrode 10. The drain electrode 18 is spaced apart from the source electrode 17 and overlaps the other end portion of the gate electrode 10. The data pad 15 is arranged at the end of the data line 19.
Still referring to FIG. 2B, a second insulation layer 31 is formed on the semiconductor layer 27 and over the patterned second metal layer. Accordingly, the first insulation layer 26, the semiconductor layer 27 and the second insulation layer 31 are formed over the gate pad 11. Moreover, the second insulation layer 31 is only formed over the drain electrode 18 and over the data pad 15.
FIG. 2C shows a step of forming contact holes 34, 35 and 36 using a third-mask process. As depicted, a photoresist 33 is deposited on the second insulation layer 31 and the exposure process is then performed using a third mask (not shown). Thus, the portions that are not irradiated are removed. After that, the exposed portions under the contact holes 34, 35 and 36 are etched. At this time, the layers (the first insulation layer 26, the semiconductor layer 27 and the second insulation layer 31) over the gate pad 11 and the second insulation layer 31 over the drain electrode 18 and gate pad 15 are simultaneously etched using dry-etching.
However, after eliminating the second insulation layer 31 over the data pad 15, the semiconductor layer 27 and first insulation layer 26 over the gate pad 11 are continuously being etched. Therefore, the data pad 15 is over-etched until all layers over the gate pad 11 are eliminated. If the data pad 15 is made of metal such as Molybdenum (Mo) or Titanium (Ti), which is easily etched by dry-etching, the portion of the data pad 15 is completely etched as shown in FIG. 2C, and thus the resistance increases due to the fact that the contact area between the data pad 15 and the electrode formed later is reduced.
Meanwhile, if the data pad 15 is made of Chrome (Cr), which is not etched very well by dry-etching, as shown in FIG. 2D the top surfaces oft he drain electrode 18 and of the data pad 15 are damaged by the plasma or the ion beam, and thus the resistance between the data pad 15 and the electrode formed later increases.
Accordingly, the present invention is directed to a method of fabricating an array substrate for use in a liquid crystal display device, which substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating an array substrate that prevents the data pad from being over-etched and from being damaged.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the principles of the present invention provide a method of manufacturing an array substrate for use in an LCD device. Such a method of fabricating an array substrate for use in a liquid crystal display (LCD) device, beneficially including: forming a first metal layer on a substrate; forming a gate line, a gate electrode and a gate pad by patterning the first metal layer; forming sequentially a first insulation layer, a semiconductor layer and a second metal layer over the patterned first metal layer and on the substrate; forming a source electrode, a data line, a drain electrode and a data pad by patterning the second metal layer; forming a second insulation layer on the patterned second metal layer and on the semiconductor layer; forming a photoresist on the second insulation layer; performing an exposure process on the photoresist using a mask; removing completely a portion of the photoresist over the gate pad after performing the exposure process; removing incompletely a portion of the photoresist over the data pad after performing the exposure process, wherein some of the photoresist over the data pad remains; etching the second insulation and semiconductor layers over the gate pad while etching the residual photoresist over the data pad; and etching simultaneously the first insulation layer over the gate pad and the second insulation layer over the data pad.
The mask that is used in irradiating the photoresist beneficially includes a half-tone pattern or a diffraction slit. The residual photoresist over the data pad has a thickness of about from 500 xc3x85 to 5000 xc3x85.
The principles of the present invention further provide a method of fabricating an array substrate for use in a liquid crystal display (LCD) device, beneficially including: forming first and second insulation layers over the gate pad; forming the second insulation layer on the data pad; depositing a photoresist on the second insulation layer, performing an exposure process on the photoresist using a mask; removing completely a portion of the photoresist over the gate pad after performing the exposure process; removing incompletely a portion of the photoresist over the data pad after performing the exposure process, wherein some of the photoresist over the data pad remains; and etching the first and second insulation layers over the gate pad while etching the residual photoresist and the second insulation layer over the data pad, wherein the residual photoresist acts as an etching stopper.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.